University of Texas Profs, Students Unveil High-Speed Chip
- By Paul McCloskey
- 05/07/07
University of Texas computer science professors and graduate students have produced a prototype high-performance processor capable of scaling to trillions of calculations per second.
The processor, known as TRIPS (for "Tera-op, Reliable, Intelligently adaptive Processing System"), outstrips the performance of current commercial technology and could be used to accelerate industrial, consumer, and scientific computing, according to the UT research team that unveiled the chip.
The team included computer science professors Stephen Keckler, Doug Burger, and Kathryn McKinley.
"The TRIPS prototype is the first on a roadmap that will lead to ultra-powerful, flexible processors implemented in nanoscale technologies," said Burger at presentation on the chip in Austin.
TRIPS is part of a class of processing architectures called Explicit Data Graph Execution (EDGE). Current multicore processors increase speed by adding more processors, which individually may not be any faster than previous processors. EDGE can process large blocks of information all at once.
"EDGE technology offers an alternative approach when the race to multicore runs out of steam," said Keckler, associate professor of computer sciences. Each TRIPS chip contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions simultaneously. Current processors run at about four operations per cycle.
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About the Author
Paul McCloskey is contributing editor of Syllabus.